This invention will be described in the environment of a digital television receiver, but it will be recognized to be applicable to a much broader range of applications utilizing peak detecting of sampled data signals.
Digital television receivers currently commercially available include analog circuitry to receive conventional broadcast TV signals and develop baseband composite TV signals. The baseband composite signal is coupled to an analog-to-digital converter (ADC) which translates the analog signals to pulse code modulated (PCM) binary signals. The PCM signals are processed in digital or binary arithmetic circuitry to separate and process the luminance and chrominance components of the composite signal. The processed digital luminance and chrominance components (color difference signals) are subsequently converted to analog signals which are coupled to analog matrixing circuitry for developing RGB color signals to drive a kinescope.
The ADC and digital processing circuitry operate synchronously responsive to a clock signal which is phase locked to the color reference burst transmitted with the composite signal. The clock signal is developed in a phase-locked-loop (PLL) circuit which develops its phase error signals from the PCM encoded burst signal. The frequency of the clock signal is typically selected to be four times the color subcarrier frequency and aligned to a particular phase of burst to facilitate digital processing. Once the clock signal is phase locked, successive samples of the burst component comprise a sequence of quadrature related samples, e.g. I, Q, -I, -Q, I, Q, etc.
In order to maximize the performance of the PLL, it is advantageous to incorporate an automatic gain control (AGC) circuit to condition the received burst signal to have a nominal amplitude. This requires an amplitude detector to measure the differential between the actual and the desired amplitude. Once the clock is phase locked to burst and if one of the clock phases is aligned with the peak of burst, the amplitude of burst is easily determined by comparing the value of the sample developed during that clock phase to a reference value. However, if none of the clock phases are aligned with the peaks of burst, but if the sampling phase .theta. of a particular sample of burst relative to the peaks of burst is known the amplitude, A, of burst may be determined from the equation EQU A=S/sin .theta. (1)
where S is the value of the particular sample. Alternatively, the burst amplitude may be determined from pairs of successive samples from the equation EQU A=.sqroot..sub.I.sup.2 +.sub.Q2 ( 2)
because of the quadrature relationship of the I and Q samples. However, the circuitry requires to compute the burst amplitude from either of these equations is undesirably complicated. In addition, during the period that the PLL circuit has not yet achieved phase lock, each of the above methods may produce particularly large errors of burst amplitude measurement.
An object of the present invention is to provide a relatively simple sampled data signal amplitude detector with improved accuracy over the above-described system.